In a step of introducing impurities to form a source region and a drain region of a MOS transistor, since the impurities are implanted into a semiconductor substrate in high concentration, the occurrence of crystal defects at the end portion of the region in the semiconductor substrate in which the impurities are implanted is often observed.
As a method of preventing the crystal defects, for example, Japanese Patent Application Laid-open Publication No. 8-97210 (Patent Document 1) has disclosed a structure in which an oxide film is interposed between a sidewall on the side surface of a gate electrode and its underlying semiconductor substrate.
Also, for example, Japanese Patent No. 3442154 (Patent Document 2) has described a technique for forming a nitrogen implantation region, which has an equal or deeper depth compared to the junction depth of a p-type source/drain region, along the whole junction region of the source/drain region so as to effectively suppress the diffusion of impurities caused by a heat treatment for electrically activating impurities.
Also, for example, Japanese Patent No. 3238551 (Patent Document 3) has disclosed a technique for suppressing leakage current, parasitic resistance, the short channel effect and the hot carrier effect as follows. That is, double sidewalls are formed on the side surfaces of a gate electrode on a semiconductor substrate, and deep n− diffusion layers are then formed in source and drain regions using the double sidewalls as a mask. Thereafter, only outer sidewalls are removed so as to leave inner L-shaped sidewalls. Subsequently, shallow n+ diffusion layers are formed in the source and drain regions. Furthermore, after the L-shaped sidewalls are removed, an n− layer for LDD is formed by ion-implantation using the gate electrode as a mask.
Also, for example, Japanese Patent Application Laid-open Publication No. 2001-15737 (Patent Document 4) has described a technique for the purpose of suppressing the short channel effect. That is, deep impurity diffusion layers which are isolated from the ends of gate electrode in source and drain regions are first formed. Thereafter, a part of sidewalls in a stacked structure of side surface of the gate electrode is removed, and shallow impurity diffusion layers adjacent to the gate electrode are later formed.
Also, for example, Japanese Patent Application Laid-open Publication No. 2000-174270 (Patent Document 5) has disclosed a technique for suppressing the increase in parasitic resistance of impurity diffusion layers and simultaneously making impurity diffusion layers shallower. That is, after sidewalls are formed on the side surface of a gate electrode, impurities are ion-implanted by using the gate electrode and the sidewalls as a mask, and then first impurity diffusion layers are formed by applying a heat treatment. Thereafter, a silicide layer is formed on the exposed surfaces of the gate electrode and the semiconductor substrate, and then the sidewalls are removed. After that, impurities are ion-implanted by using the gate electrode as a mask and heat treatment is performed, whereby, second impurity diffusion layers shallower than the first diffusion layers are formed.